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Astera Labs

Manager Design Verification

  • Tel Aviv-Yafo, Tel Aviv District, Israel
  • Full-time
  • Posted
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Skills

  • Embedded Systems
  • Leadership
  • Physical Design
  • RTL Design
  • Teamwork
  • Verilog

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Manager Design Verification  

Tel Aviv District, Israel  

Astera Labs is seeking an experienced Manager, Design Verification to lead a team responsible for verifying the next generation of connectivity silicon powering the world's largest AI clusters. In this role, you will drive verification strategy and execution for complex SoC and IP designs supporting PCIe, CXL, Ethernet, UALink, and other advanced interconnect technologies.  

You will partner closely with Architecture, Design, Firmware, Post-Silicon Validation, and Program Management teams to ensure first-pass silicon success while scaling methodologies and processes across a growing organization.  

Key Responsibilities  

Verification Leadership  

•Lead and mentor a team of Design Verification engineers.  
•Define verification strategies, schedules, and execution plans for IP, subsystem, and SoC-level verification.  
•Drive verification planning, resource allocation, and project execution to meet aggressive tapeout schedules.  

Verification Development & Execution  

•Own verification sign-off criteria, coverage metrics, and quality standards.  
•Develop and review UVM/SystemVerilog testbenches, checkers, scoreboards, and verification components.  
•Collaborate with Design and Architecture teams to ensure comprehensive verification of specifications and microarchitectures.  

Methodology & Quality  

•Establish and improve verification methodologies, infrastructure, and best practices.  
•Establish reusable verification frameworks across multiple projects.  
•Ensure high-quality metrics-driven verification sign-off.  

Cross-Functional Collaboration  

•Work closely with RTL Design, DFT, Firmware, Post-Silicon Validation, and Physical Design teams.  
•Support bring-up and debug activities by correlating pre-silicon and post-silicon results.  
•Contribute to technical roadmap discussions and verification planning for future products.  

 

Basic Qualifications  

•Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.  
•8+ years of ASIC/SoC verification experience.  
•4+ years of technical leadership or people management experience.  
•Strong expertise in SystemVerilog and UVM.  
•Experience creating complex verification environments from architecture through sign-off.  
•Familiarity with SoC architectures and high-speed interfaces.  

 

Preferred Qualifications  

•Experience verifying PCIe Gen5/Gen6, CXL, Ethernet, UCIe, UALink, or similar protocols.  
•Knowledge of advanced SoC architectures and coherent fabrics.  
•Proven track record of shipping complex silicon products successfully.  

 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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