๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฏ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฏ๐ฌ-๐ฑ๐ฌ ๐๐ฃ๐)
Experience: 6+ yrs
Location: Hyderabad, Telangana, India
Job Type: Full-time
We are looking for experienced ASIC RTL Design professionals to join the semiconductor engineering team at Senior Engineer through Architect levels. This role is suited for highly skilled engineers who have strong expertise in RTL design, digital logic, and ASIC development and are looking to contribute to the architecture and implementation of complex semiconductor products.
You will be involved across key stages of the RTL design lifecycle, from understanding architectural specifications and developing microarchitecture to writing synthesizable RTL, supporting verification, and resolving design issues. Depending on your experience level, you may also take ownership of design blocks, provide technical leadership, and contribute to architectural decisions.
Requirements
Key Responsibilities
โขDevelop high-quality, synthesizable RTL designs based on architectural and microarchitectural specifications.
โขTranslate system requirements into efficient digital hardware implementations.
โขDesign and implement complex digital logic blocks for ASIC products.
โขParticipate in microarchitecture definition, design reviews, and technical discussions.
โขDevelop clean, reusable, and scalable RTL using industry-standard design methodologies.
โขCollaborate with verification teams to define design requirements and resolve functional issues.
โขDebug RTL and simulation issues and work closely with verification teams to identify root causes.
โขSupport synthesis, timing analysis, linting, CDC, and other design-quality activities.
โขAnalyze and optimize designs for performance, power, area, and reliability .
โขWork closely with physical design and implementation teams to address design constraints and integration challenges.
โขReview specifications, RTL, design documentation, and technical deliverables for quality and completeness.
โขContribute to improving RTL design methodologies, coding standards, and development processes.
โขFor senior and architect-level roles, provide technical leadership, mentor engineers, and drive complex design initiatives.
โขParticipate in cross-functional technical reviews and contribute to architectural decisions.
What Makes You a Great Fit
โข6+ years of hands-on experience in ASIC RTL design or digital hardware development.
โขStrong understanding of digital design fundamentals, RTL coding, and ASIC design methodologies .
โขProven experience developing synthesizable RTL for complex digital systems.
โขStrong proficiency in Verilog/SystemVerilog and RTL design practices.
โขExperience with simulation, debugging, linting, CDC, synthesis, and other RTL design-quality processes.
โขGood understanding of ASIC development flows and collaboration across design, verification, and physical design teams.
โขAbility to analyze complex technical problems and develop efficient, reliable solutions.
โขStrong understanding of design trade-offs involving power, performance, and area (PPA) .
โขExcellent problem-solving, communication, and technical documentation skills.
โขAbility to work independently while collaborating effectively with cross-functional engineering teams.
โขSenior Engineer candidates should demonstrate ownership of complex RTL blocks, while Architect-level candidates should have strong experience in microarchitecture, technical leadership, and design strategy .
โขA strong passion for semiconductor technology and the ability to continuously learn and adapt to evolving ASIC design methodologies.